Physical Design Engineer Intern
AmbarellaAdded 3h ago
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Quick summaryby newgrad.ai
What you'll do
- Execute physical design tasks from netlist through GDSII.
- Perform floor-planning, placement, and routing for AI SoCs.
- Conduct timing, signal integrity, and power analysis.
- Complete formal verification and physical layout checks.
What they're looking for
- Ability to manage block or full-chip implementation.
- Proficiency in static timing and physical verification tools.
- Experience with EM/IR analysis and layout design.
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Job Description
The Physical Design Engineer will be an integral part of the physical design team with all aspects of physical design implementation and verification tasks for Ambarella’s cutting edge low power AI SoC from Netlist to GDSII.
The Physical Design Engineer will be responsible for the following areas throughout all phase of SoC implementation process; floor-planning, auto place and route, static timing analysis, eco implementation, signal integrity analysis, EM/IR analysis, formal verification, and physical layout verification (LVS/DRC/DFM) at block and/or full chip level.
From Ambarella's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.
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