Verification Engineer Intern
AmbarellaAdded 1mo ago
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Quick summaryby newgrad.ai
What you'll do
- Develop test benches and write debugging tests for RTL logic
- Create random test generators for automated intelligent test generation
- Write coverage monitors, checkers, and assertions with statistics collection
- Build tools and scripts for simulation stimulus and performance analysis
What they're looking for
- Near completion of master's degree with strong VLSI design interest
- Experience with Verilog, SystemVerilog, UVM, C/C++, Perl, Python, or assembly
- Self-motivated and creative with ability to learn skills quickly
- Capable of delivering assignments on time and presenting work
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Job Description
Ambarella has some exciting internship opportunities for self-motivated and creative students near completion of their master's degree. We are looking for talented engineers who possess a strong interest in VLSI design, programming and computer architecture.
Ambarella designs complex SoCs which include custom DSP and computer vision blocks, CPUs and co-processors. Some example responsibilities will include:
- Develop test benches (or parts thereof), write and debug tests and RTL logic.
- Write Random Test Generators to automatically and intelligently generate the tests.
- Write coverage monitors, checkers, assertions and collect statistics.
- Create tools, scripts and utilities to aid in creating stimulus and analyzing the results of simulations, including performance measurements.
The internship program requires some exposure to the programming and scripting languages like Verilog, System Verilog, UVM, C and C++, Perl, Python or assembly code. We expect that interns will be able to pick up missing skills quickly, deliver their assignments on time, and present their work at the end of the program.
From Ambarella's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.
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