R
CPU RTL Microarchitecture/Design Engineer - Full Time
RosaicLabsAdded 4h ago
Santa Clara, CAFull-timeEntry
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What you'll do
- Create and implement CPU functional blocks from microarchitecture specs.
- Write, debug, and optimize RTL code using SystemVerilog or Verilog.
- Balance performance, power, and area metrics through design improvements.
- Collaborate with verification and physical design teams on project goals.
What they're looking for
- Bachelor’s or Master’s degree in engineering or computer science.
- Knowledge of computer architecture, including memory systems or execution logic.
- Practical experience with Verilog, RTL simulation, and debugging.
- Proficiency in Python, Perl, Tcl, or C/C++ for automation tasks.
Summarized by newgrad.ai from RosaicLabs's public posting. Check the original for full details before you apply.
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