RTL Power Macromodeling Engineer Intern

What you'll do

• Develop and validate IP-level power macromodels for AI memory components.
• Extract power features from RTL, SystemC, and C simulations.
• Calibrate models using synthesis, circuit-level references, and measured data.
• Integrate validated models into trace-driven power and thermal simulators.

What they're looking for

• MS or PhD student in Electrical Engineering, Computer Science, or related fields.
• Proficiency in Verilog, SystemVerilog, SystemC, C++, or Python.
• Knowledge of CMOS dynamic and leakage power and circuit abstraction.
• Must have at least one academic term remaining.

Pay and perks

• Hourly base pay rate of $28–$68 USD.
• Includes relocation and housing stipends for eligible interns.