DRAM Technology Physical Design and Block-Level PPA Optimization Intern

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes.

As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment.

• Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement.

• Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities.

• Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues.