Astera Labs is seeking a Digital Design Intern to contribute to the development of ASIC and digital hardware blocks. You will gain hands-on experience with RTL implementation, design-quality checks, simulation and elaboration, clock-domain crossing analysis, synthesis, and the collaboration required to move a design from specification toward verification and physical-design handoff.
You will work on a scoped digital-design project with guidance from experienced engineers. Your work will combine learning the design methodology with making practical contributions to readable, reusable, and verifiable RTL.
What you will do
Learn the project RTL structure, coding methodology, build flow, design tools, and review process.
Implement, modify, and review synthesizable Verilog or SystemVerilog RTL for digital logic blocks and interfaces.
Translate block requirements into clear module structure, state machines, datapaths, control logic, registers, and interfaces.
Generate or update RTL, filelists, register-related collateral, and configuration files using the project flow.
Create or improve directed simulations, simple testbenches, assertions, and checks to exercise block functionality and corner cases.
Run compile and elaboration, lint, clock-domain crossing, and synthesis flows; inspect reports and summarize issues.
Debug RTL, tool warnings, constraint issues, and simulation mismatches with support from design and verification mentors.
Apply coding guidelines, naming conventions, hierarchy rules, reset practices, and reusable design-IP conventions during implementation and review.
Collaborate with design verification, physical design, DFT, firmware, and systems engineers on interfaces, assumptions, debug visibility, and handoff readiness.
Document design decisions, test results, open issues, and handoff information; present the completed project and lessons learned.
What you bring
Enrollment in a bachelor's, master's, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
Coursework, research, or project experience in digital logic, computer architecture, embedded systems, ASIC design, FPGA design, or hardware description languages.
Programming or hardware-description-language experience with Verilog, SystemVerilog, VHDL, C, C++, Python, or a comparable language.
Familiarity with digital design concepts such as flip-flops, finite-state machines, clocks, resets, datapaths, registers, timing, and interfaces.
Familiarity with Linux development environments, Git, command-line tools, debugging, and technical documentation.
Ability to reason carefully about requirements, waveforms, tool reports, and corner cases.
Strong ownership, curiosity, practical judgment, and willingness to collaborate across engineering functions.
Exposure to lint, CDC, synthesis, formal verification, timing, or other design-quality and signoff checks.
Familiarity with tools such as VCS, SpyGlass, Design Compiler, PrimeTime, or comparable EDA tools.
Understanding of clock-domain crossing patterns, including synchronizers, handshakes, asynchronous FIFOs, gray-coded pointers, and CDC constraints.
Experience with CSR or register-map generation, parameterized modules, configuration variants, or debug and observability features.
Experience reading waveforms and reports, triaging failures, and communicating a clear technical recommendation.
Internship experience and compensation
This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.
Equal opportunity
Astera Labs is an equal opportunity employer committed to fostering a diverse and inclusive workplace. We encourage anyone with relevant experience to apply.
From Astera Labs's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.
