Astera Labs develops purpose-built connectivity solutions for rack-scale AI infrastructure. Our Intelligent Connectivity Platform brings together high-performance connectivity technologies for AI, cloud, server, and networking systems.
The role
As a Digital Design Intern in Toronto, you will contribute to the design of digital logic for Astera Labs connectivity products. You will work with design engineers to understand specifications, develop and modify RTL, run design-quality checks, and debug simulation or tool results across the hardware-design flow.
This internship is an opportunity to build hands-on experience with ASIC digital design, computer architecture, RTL development, and the tools and practices used to take complex connectivity IP from specification toward implementation.
What you'll do
Translate design specifications and interface requirements into clear RTL implementations.
Develop, modify, and review Verilog or SystemVerilog RTL for digital IP blocks and their supporting logic.
Work with design engineers on microarchitecture, registers, interfaces, clocks, resets, and control logic.
Run compile, lint, simulation, synthesis, or other design-flow checks and investigate warnings, errors, and generated reports.
Use Linux command-line tools, Git, scripts, and established repository conventions to manage design work.
Collaborate with design-verification engineers to clarify intent, reproduce issues, and improve design quality.
Add or update assertions, constraints, documentation, and design metadata when appropriate.
Learn and apply clock-domain-crossing, reset, signal-integrity, and hardware/software interface concepts relevant to the design.
Document design decisions, debug findings, and implementation details for the broader engineering team.
What you bring
Basic qualifications
Currently pursuing a bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Coursework, project, research, or hands-on experience with digital logic, computer architecture, RTL, or ASIC design.
Programming or hardware-description-language experience in Verilog, SystemVerilog, C/C++, Python, or a comparable language.
Familiarity with Linux development environments, command-line tools, and Git or another source-control system.
Strong analytical and debugging skills, with an interest in understanding how digital hardware is implemented.
Strong written and verbal communication, organization, and time-management skills.
A hands-on work ethic, curiosity, learning agility, and ability to take ownership of assigned deliverables.
Preferred qualifications
Experience developing RTL modules, finite-state machines, datapaths, control logic, or register interfaces.
Familiarity with simulation, lint, synthesis, waveform-debug, or ASIC design tools.
Exposure to clock-domain crossing, reset design, assertions, formal verification, or emulation.
Familiarity with AXI, APB, PCIe®, CXL®, memory systems, fabrics, controllers, or other high-speed digital interfaces.
Experience using Python, Tcl, shell scripting, or Make-based workflows to automate design tasks and analyze results.
Interest in the design of connectivity products used in AI, cloud, server, or networking systems.
Equal opportunity
Astera Labs is committed to an inclusive workplace and considers qualified applicants without regard to protected characteristics under applicable law.
From Astera Labs's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.
