Device Engineering Intern, ULP CMOS (Fall 2026)
GlobalFoundriesAdded 1d ago
New York, NY +1 moreInternship
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ProJev · full postingWhat you'll do
- Design device test chip layouts for ULP CMOS technology development
- Submit and analyze inline and bench electrical test results
- Automate device analysis to improve standardization and efficiency
- Collaborate with technology development teams on silicon transistor optimization
What they're looking for
- At least sophomore pursuing Bachelor's in Electrical Engineering, Materials Science, or related field
- Minimum 3.0 GPA and good academic standing
- Fluent in English (written and verbal)
- Ability to work at least 40 hours per week
Pay and perks
- $20.00 - $40.00 per hour, determined by qualifications and location
- One-on-one mentorship and professional development opportunities
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