# CPU RTL Microarchitecture/Design Engineer - Full Time at RosaicLabs

- Company: RosaicLabs
- Location: Santa Clara, CA
- Type: Full-time · Entry
- Posted: 2026-09-29
- Apply: https://jobs.lever.co/rosaiclabs/addeaa7f-f51c-45a8-b10c-af945db9ce53
- Page: https://newgrad.ai/jobs/cpu-rtl-microarchitecture-design-engineer-full-time-c5993d9b

## Posting

What you'll do:

- Create and implement CPU functional blocks from microarchitecture specs.
- Write, debug, and optimize RTL code using SystemVerilog or Verilog.
- Balance performance, power, and area metrics through design improvements.
- Collaborate with verification and physical design teams on project goals.

What they're looking for:

- Bachelor’s or Master’s degree in engineering or computer science.
- Knowledge of computer architecture, including memory systems or execution logic.
- Practical experience with Verilog, RTL simulation, and debugging.
- Proficiency in Python, Perl, Tcl, or C/C++ for automation tasks.

Summarized by newgrad.ai from RosaicLabs's public posting. Check the original for full details before you apply.

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