# CPU Design Verification Engineer Intern at RosaicLabs

- Company: RosaicLabs
- Location: Santa Clara, CA +1 more
- Type: Internship · Internship
- Posted: 2026-10-28
- Apply: https://jobs.lever.co/rosaiclabs/11a93b50-2472-4ec9-85d9-c99a3a17405e/apply
- Page: https://newgrad.ai/jobs/cpu-design-verification-engineer-intern-89d2a6e2

## Summary by newgrad.ai

What you'll do:

- Create verification plans for CPU cores and cache systems.
- Develop and debug SystemVerilog and UVM testbenches.
- Analyze functional coverage and resolve design failures.
- Document verification environments and participate in technical reviews.

What they're looking for:

- Students pursuing a BS or MS in engineering or science.
- Knowledge of digital logic, microarchitecture, and RTL design.
- Experience with SystemVerilog, UVM, and constrained-random verification.
- Proficiency in Python, Perl, or Tcl scripting.

## Posting

Join our hardware team as an intern or co-op verifying the CPU core and cache hierarchy, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

### What you'll do

- Work with your mentor to develop verification plans for the CPU core and cache hierarchy
- Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
- Build tests, scoreboards, and reference models, and close functional and code coverage
- Triage and root-cause failures with RTL designers, with mentorship from senior engineers
- Participate in design and verification reviews and document your verification environment and results

### Requirements

- Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
- Familiarity with verifying processor designs, such as: a modern ISA; out-of-order execution and memory ordering; cache coherency and virtual memory
- Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
- Understanding of the end-to-end ASIC design flow and general VLSI concepts
- Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

From RosaicLabs's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.

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