ASIC Engineer Early Career Intern

What you'll do

• Design and implement RTL for digital logic blocks using Verilog or SystemVerilog.
• Develop verification environments to validate design functionality and coverage.
• Support synthesis, timing analysis, and physical design flows.
• Collaborate with cross-functional teams to take features from specification to silicon.

What they're looking for

• Students graduating by May 2027 in engineering or computer science fields.
• Knowledge of digital design concepts like sequential logic and timing.
• Familiarity with hardware description languages such as Verilog, SystemVerilog, or VHDL.

Pay and perks

• Annual salary: $116,100 in Seattle or Austin; $133,600 in Cupertino.
• Includes 401(k) matching, mental health support, and medical advice services.