# ASIC Design Engineer Intern at Ambarella

- Company: [Ambarella](https://ambarella.com)
- Location: United States
- Type: Internship · Internship
- Posted: 2026-08-26
- Apply: https://ambarella.wd108.myworkdayjobs.com/ambarella/job/US-Headquarters/ASIC-Design-Engineer-Intern_JR100357
- Page: https://newgrad.ai/jobs/asic-design-engineer-intern-c9f13018

## Summary by newgrad.ai

What you'll do:

- Design and implement video compression, image processing, and AI accelerator logic in Verilog and SystemVerilog.
- Synthesize and optimize RTL for timing, area, and power constraints.
- Develop testbenches, test cases, and perform functional verification and coverage analysis.
- Participate in chip bring-up and testing activities.

What they're looking for:

- Master's degree in Electrical, Electronics, or Computer Engineering with 0-5 years experience.
- Strong knowledge of computer architecture, logic design, and VLSI design fundamentals.
- Proficiency in SystemVerilog, Verilog, Perl, and scripting languages.
- Understanding of design verification, functional coverage, and logic synthesis.
- Assembly language programming capability and strong communication skills.

## Posting

### AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

### Job Description

### Position Responsibilities:

- Designing and implementing video compression logic, image processing logic, neural network and AI accelerator logics, and processor cores, in Verilog and System Verilog.

- Logic design, implementation, and verification using Verilog, System Verilog, and any required programing and scripting languages.

- Synthesize and optimize RTL for timing, area and power.

- Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.

- Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.

- Developing front-end methodologies and tool flows.

- Participating in chip bring-up and testing.

### Requirements:

- Master's degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.

- Good understanding of computer architecture, logic design and VLSI design.

- Knowledge of System Verilog, Verilog, and Perl.

- Knowledge of design verification, and functional coverage.

- Ability to program scripting languages and the ability to write assembly language programs.

- Strong communication skills and a good team player.

- Knowledge of logic synthesis and timing closer

From Ambarella's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.

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More new-grad and intern roles: https://newgrad.ai/llms.txt