# AI Accelerator Design Verification Engineer Intern at RosaicLabs

- Company: RosaicLabs
- Location: Santa Clara, CA +1 more
- Type: Internship · Internship
- Posted: 2026-10-28
- Apply: https://jobs.lever.co/rosaiclabs/8e3e00f8-5b06-450c-bb63-5cc4fc3136ab/apply
- Page: https://newgrad.ai/jobs/ai-accelerator-design-verification-engineer-intern-3fc2cdd1

## Summary by newgrad.ai

What you'll do:

- Create verification plans and develop SystemVerilog/UVM testbenches for hardware blocks.
- Build reference models and scoreboards to achieve functional and code coverage.
- Collaborate with designers to debug failures and document verification results.

What they're looking for:

- Students pursuing a BS or MS in engineering or computer science.
- Coursework in digital logic, microarchitecture, or constrained-random verification.
- Practical experience with SystemVerilog, UVM, and scripting languages like Python.
- Knowledge of ASIC design flows and accelerator architectures like SIMD or DMA.

## Posting

Join our hardware team as an intern or co-op verifying the accelerator, with hands-on ownership of verification environments from test plan through coverage closure and bring-up.

Get hands-on exposure to chip design and verification — perfect for EE/CompE students curious about how it all comes together.

### What you'll do

- Work with your mentor to develop verification plans for the accelerator
- Write and debug SystemVerilog/UVM testbenches, checkers, and stimulus for your assigned block
- Build tests, scoreboards, and reference models, and close functional and code coverage
- Triage and root-cause failures with RTL designers, with mentorship from senior engineers
- Participate in design and verification reviews and document your verification environment and results

### Requirements

- Working toward BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field
- Recently completed coursework in digital design and verification, covering at least one of: computer microarchitecture; digital logic and RTL design; constrained-random and coverage-driven verification
- Familiarity with verifying accelerator designs, such as: parallel datapaths and SIMD / SIMT / vector processing; numerical formats and computer arithmetic; data movement over DMA and memory interfaces
- Hands-on SystemVerilog experience, including: testbench development (UVM preferred); assertions and functional coverage
- Understanding of the end-to-end ASIC design flow and general VLSI concepts
- Scripting experience (Python, Perl, or Tcl) for regression automation; C/C++ a plus

From RosaicLabs's public posting, laid out for reading by newgrad.ai with the wording unchanged. Check the original before you apply.

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