Advanced DV Engineering Intern
About the role
Astera Labs is seeking an Advanced Design Verification Engineering Intern to help validate complex ASIC and system designs before silicon is available. You will work with design verification engineers to develop tests, improve verification environments, analyze coverage, debug failures, and apply simulation and formal methods to assess whether designs meet their specifications.
This internship is intended for a student who is ready to go beyond running existing tests and contribute to verification strategy, reusable infrastructure, and difficult debug problems. You will own a scoped project with guidance from experienced engineers and deliver verification work in a usable state.
What you will do
- Translate architectural, microarchitectural, interface, and product requirements into verification scenarios, test plans, coverage goals, and checkers.
- Develop and maintain SystemVerilog and UVM testbench components, sequences, tests, monitors, scoreboards, functional coverage, and end-of-test checks.
- Add directed, constrained-random, error-injection, compliance, stress, and corner-case tests for blocks, subsystems, or top-level functionality.
- Configure and run simulations and regressions using project submission flows, manifests, plusargs, firmware images, and test definitions.
- Debug failures by correlating logs, UVM messages, assertions, register reports, firmware output, and Verdi or DVE waveforms.
- Triage regression failures, distinguish design issues from testbench or environment issues, reproduce failures, and communicate actionable root-cause analysis.
- Analyze functional and code coverage, identify untested scenarios or coverage gaps, and propose targeted tests or verification improvements.
- Write, review, and debug SystemVerilog assertions and coverage properties that capture design intent and interface behavior.
- Support formal verification flows such as design compile, reset analysis, automatic property extraction, dead-code analysis, and formal property verification.
- Create or improve Python, Tcl, or other automation that simplifies test generation, regression execution, result parsing, coverage analysis, or failure triage.
- Collaborate with RTL design, firmware, emulation, physical design, and systems engineers to clarify assumptions and close verification issues.
- Document test intent, debug findings, coverage status, known limitations, and handoff information; present the completed project and recommendations.
What you bring
- Enrollment in a bachelor's, master's, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
- Coursework, research, or project experience in digital logic, computer architecture, ASIC/FPGA design, verification, embedded systems, or hardware/software integration.
- Programming or verification experience with SystemVerilog, Verilog, C, C++, Python, or a comparable language.
- Familiarity with digital design concepts, simulation, testbenches, interfaces, clocks, resets, registers, and debugging from waveforms or logs.
- Familiarity with Linux development environments, Git, command-line tools, and technical documentation.
- Ability to reason from a specification, investigate failures systematically, and communicate clear technical conclusions.
- Strong ownership, curiosity, practical judgment, and willingness to collaborate across engineering functions.
Preferred qualifications
- Experience with UVM components, sequences, virtual sequences, agents, monitors, scoreboards, reference models, or functional coverage.
- Familiarity with SystemVerilog Assertions, constrained-random testing, coverage-driven verification, error injection, or compliance testing.
- Exposure to verification IP and protocols such as PCIe, CXL, AXI, or other high-speed and control interfaces.
- Experience with Verdi, DVE, VCS, Questa, Xcelium, VC Formal, or comparable simulation and formal tools.
- Familiarity with formal concepts such as assumptions, assertions, covers, counterexamples, reset analysis, dead-code analysis, or automatic property extraction.
- Experience managing regressions, parsing results, debugging intermittent failures, or running jobs on a compute cluster or CI system.
Internship experience and compensation
This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation.
Equal opportunity
Astera Labs is an equal opportunity employer committed to fostering a diverse and inclusive workplace. We encourage anyone with relevant experience to apply.
